| 摘要 |
A substrate based package design for semiconductor chips is disclosed which reduces ground loop inductance. The design includes a substrate having a metal layer providing electrical interconnections. The metal layer includes a first conductive area adapted to provide an electrical ground, and a second conductive area adapted to provide an electrical connection to a power supply voltage. The first conductive area has a plurality of first conductive finger extensions providing electrical connections to vias for the electrical ground, and the second conductive area has a plurality of second conductive finger extensions providing electrical connections to vias for the power supply voltage. The first finger extensions and the second finger extensions are interlaced with each other.In accordance with another aspect of the invention, an internal conductive ring for ground is provided, with a concentric outer conductive ring for power supply connections. Further, each respective ring has conductive finger extensions in an interlaced comb configuration.
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