| 摘要 |
A microprocessor configured to reduce variance in the length of variable length instructions by compressing multiple prefix bytes into a single byte is disclosed. The microprocessor is configured with a predecode unit and an instruction cache. The predecode unit is configured to receive variable length instructions, each having a variable number of prefix bytes. The predecode unit is configured to detect the prefix bytes and compress them into one compressed prefix byte for each instruction. The instruction cache is coupled to the predecode unit and is configured to receive and store the instructions and compressed prefix bytes from the predecode unit. The instruction cache may be configured to output one of the instructions and any corresponding compressed prefix bytes in response to receiving a fetch address. A computer system, method, and software program configured to compress prefix bytes are also disclosed.
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