发明名称 Multiprocessor system bus with system controller explicitly updating snooper cache state information
摘要 Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy with a coherency state of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state information appended to the combined operation and the snoop responses, whether a coherency upgrade is possible. If so, the combined response logic selects a snooper storage device to upgrade the coherency state of a respective cache line corresponding to the victim, and appends an upgrade directive to the combined response. The snooper selected to upgrade the coherency state of a cache line corresponding the victim may be randomly chosen or, as an optimization, be chosen for having the highest LRU position for the respective cache line.
申请公布号 US6275909(B1) 申请公布日期 2001.08.14
申请号 US19990368226 申请日期 1999.08.04
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ARIMILLI RAVI KUMAR;DODSON JOHN STEVEN;GUTHRIE GUY LYNN;JOYNER JODY B.;LEWIS JERRY DON
分类号 G06F12/08;(IPC1-7):G06F13/00 主分类号 G06F12/08
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