| 摘要 |
A circuit arrangement for reducing a variable, in particular pulsed input voltage (Uein) to an operating voltage Uz, Uarb to be delivered to an evaluation circuit (10), in which the input voltage Uein can be reduced, in accordance with a division factor (F) made available by at least one voltage divider (R1, R3, T1, R4; R7, R8, R2), to obtain the operating voltage Uz, Uarb, in which the at least one voltage divider (R1, R3, T1, R4; R7, R8, R2), can be regulated in such a way that the division factor (F) can be increased with an increasing input voltage Uein and can be decreased with a decreasing input voltage Uein.
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