| 摘要 |
A row decoder (10) for a video display system (12) wherein row output lines (28) of a row predecoder (20) are physically arranged such that adjacent iterations of the output lines (28) will generally not be switching simultaneously where addressing of the output lines (28) is sequential according to numbering and application. A ground trace (32) is provided between iterations of the output lines (28) which will be switching simultaneously. The output lines (28) provide input to a decoding circuit (34) within the row decoder (10). A plurality iterations of predecoder subcircuits (21) each having a compliment of the output lines (28) is to provided such that all of the rows of a pixel array (14) can be addressed.
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