发明名称 APPARATUS FOR DETECTING ERROR OF SYNCHRONOUS CLOCK AND ATM SWITCH USING THE SAME
摘要 PURPOSE: An apparatus for detecting an error of a synchronous clock and ATM(Asynchronous Transfer Mode) switch using the same is provided to detect an error according to a jitter of a synchronous signal, detect a wander phenomenon, and perform a normal clock monitoring function irrespective of a metastability of a circuit element. CONSTITUTION: A counter(401-1) divides an inputted clock and output a frequency division signal with a m-times period of a period of the input clock to provide the frequency division signal to a one shot generator(403-1) directly and provides the frequency division signal to a one shot generator(403-2) through a delay buffer(404). The one shot generators(403-1,403-2) are synchronized to a monitoring reference clock(Clock-3) generated in a synchronous clock source in a switch module and generates a one-shot pulse throughout one period of the clock(clock-3) on the basis of a rising transition time of a monitoring reference clock primarily generated after a rising transition time of a m-divided signal of a monitoring object clock outputted from the counter(401-1). Initialized modulo-m binary counters(401-2,401-3) outputs one-shot pulses corresponding to one period of the clock(clock-3) through output terminals after an m-period of the clock(clock-3). One-shot pulses generated in the one shot generators(403-1,403-2) and one-shot pulses generated in the one-shot generators(401-2,401-3) are compared through exclusive OR gates(406-1,406-2). The compared signal is sampled by an m-period sample circuit having multiplexers(400-4,400-5) and flip-flops(402-2,402-3) and the sampled signal is judged by an NAND gate(407).
申请公布号 KR20010075868(A) 申请公布日期 2001.08.11
申请号 KR20000002765 申请日期 2000.01.21
申请人 KOREA ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE;KOREA TELECOM 发明人 JUN, YONG IL;JUNG, UI SEOK
分类号 H04L12/50;(IPC1-7):H04L12/50 主分类号 H04L12/50
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