发明名称 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce decrease of a threshold voltage caused by short channel effect, deterioration of subthreshold characteristic, decrease of punch through withstanding voltage, etc., and can realize microstructure by having different threshold voltages in the same chip and constituting the entire device by using surface channel transistors, and a manufacturing method of a semiconductor device wherein manufacturing is enabled without needing an additional process and a mask. SOLUTION: In this semiconductor device, an N well diffusion layer 2 and a P well diffusion layer 3 which are arranged adjacently are disposed. A P gate PMOS transistor 100 having a P-type gate electrode 71 and an N gate PMOS transistor 101 having an N-type gate electrode 72 are formed in the same N well diffusion layer 2. A P gate NMOS transistor 200 having a P-type gate electrode 71 and an N gate NMOS transistor 201 having an N-type gate electrode 72 are formed in the same P well diffusion layer 3.
申请公布号 JP2001217321(A) 申请公布日期 2001.08.10
申请号 JP20000023208 申请日期 2000.01.31
申请人 NEC CORP 发明人 NAKAUCHI OSAMU
分类号 H01L27/092;H01L21/8238;(IPC1-7):H01L21/823 主分类号 H01L27/092
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