发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten phase pull-in time when a frequency is almost matched but a phase is deviated almost >=90 deg. in a PLL circuit. SOLUTION: A >=90 deg. phase deviation detector 7 is provided for judging whether the phase is deviated almost >=90 deg. or not and when it is detected that the phase is deviated almost >=90 deg., by charging a current to a loop filter 5, a gain is equivalently increased rather than ordinary. Thus, pull-in time can be shortened.
申请公布号 JP2001217710(A) 申请公布日期 2001.08.10
申请号 JP20000024558 申请日期 2000.02.02
申请人 NEC CORP 发明人 TANAKA MIKIKO
分类号 H03L7/095;H03L7/08;H03L7/087;H03L7/093;H03L7/10;H03L7/107;H03L7/113 主分类号 H03L7/095
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