NET LIST EXTRACTING METHOD FOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a net list extracting method for an integrated circuit which can reduce the amount of information on a net list and shorten the time of verification by the net list. SOLUTION: By this net list extracting method, information on connections among elements is extracted from a layout pattern, designed so that blocks have hierarchical structure, while the hierarchical structure is held; and a dummy element is formed between input and output terminals in a block positioned in a specific layer (step S25) and then only the input and output terminals are extracted without extracting elements in the block.