发明名称 TWO-MULTIPLYING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a two-multiplying circuit, which can generate multiplied signals corresponding to input signals over a wide range and which is reduced in circuit scale and power consumption. SOLUTION: The two-multplying circuit comprises a delay generation part 1, which inputs a subclock and generates a two-multipled clock 105 according to the value of delay data 112, a delay quantity correction part 2 which corrects and holds the delay data 112, a rise detection part 3 which generates a rise detection signal 107, and a duty detecting part 4 which generates a decision signal 110 according to the duty ratio of the two-multiplied clock 105. After the delay data 112 are corrected, the delay quantity correction part 2, rise detection part 3, and duty detecting part 4 stop operating and a main oscillator stops oscillating. A system, equipped with the two-multiplying circuit, operates according to the two-multiplied clock 105.
申请公布号 JP2001217688(A) 申请公布日期 2001.08.10
申请号 JP20000025070 申请日期 2000.02.02
申请人 NEC MICROSYSTEMS LTD 发明人 ISHIHARA KUNIYASU
分类号 H03K5/00;(IPC1-7):H03K5/00 主分类号 H03K5/00
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