发明名称 ADDRESS LINE FAULT DETECTOR FOR MEMORY, METHOD THEREFOR AND RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To provide a technique for detecting a fault generated on a line for the address input of a memory. SOLUTION: A CPU 102 inputs an address through an address line 103 to the memory 101. A fault generated on the address line 103, prescribed data different from the others are written to a predetermined address, the data of the address specified by changing a logic value by the unit of the address line 103 are read from the address and the read are compared with the prescribed data. By the comparison, it is judged that the fault is generated in the address line 103 for which the prescribed data are read even when the logic value is changed.
申请公布号 JP2001216202(A) 申请公布日期 2001.08.10
申请号 JP20000022407 申请日期 2000.01.31
申请人 FUJITSU KIDEN LTD 发明人 YONEYAMA CHIKAKO
分类号 G06F12/16;G11C29/00;G11C29/10;(IPC1-7):G06F12/16 主分类号 G06F12/16
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