发明名称 |
Shift register circuit capable of reducing consumption of power with reduced capacitive load of clock signal line and image display device including it |
摘要 |
There is provided a shift register circuit of a wide operation margin capable of reducing a capacitive load of a clock signal line, reducing a load of external circuits and achieving consumption power reduction and cost reduction with a simple construction, and an imaging display device including it. A plurality of serially connected register blocks BLK2 has a D-type flip-flop DFF1 that operates in synchronization with a clock signal, transfer gates TG11 and TG12 for controlling clock signals CK and /CK supplied to the D-type flip-flop DFF1 and an exclusive-OR circuit XOR1 that outputs a control signal to the transfer gates TG11 and TG12 so that the transfer gates are brought into an ON-state only in a specified period during which the output of the D-type flip-flop DFF1 changes i.e. when the input signal level and the output signal level of the D-type flip-flop DFF1 differ from each other.
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申请公布号 |
US2001011987(A1) |
申请公布日期 |
2001.08.09 |
申请号 |
US20010775167 |
申请日期 |
2001.02.01 |
申请人 |
KUBOTA YASUSHI;WASHIO HAJIME |
发明人 |
KUBOTA YASUSHI;WASHIO HAJIME |
分类号 |
G02F1/133;G09G3/18;G09G3/20;G09G3/36;G11C8/04;G11C19/00;G11C19/28;H04N5/66;(IPC1-7):G09G3/36;H03K19/017 |
主分类号 |
G02F1/133 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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