| 摘要 |
<p>A data transaction access system for an embedded microprocessor coupled to a PCMCIA bus device. A bus master and a host bus adapter are couple d to a local bus for enabling communication between the bus master and a PCMCIA device. The PCMCIA device is coupled to the host bus adapter via a PCMCIA bus. The bus master uses the local bus to communicate with the PCMCIA device via the host bus adapter. A wait register is coupled to the host bus adapter to receive a delay input from the PCMCIA device describing a latency period of the device when completing a data transaction. Where the latency period described by the delay input is less than a predetermined amount, the host bus adapter is configured to insert wait states into the data transaction of the bus master. When the latency period is greater than the predetermined amount, the host bus adapter is configured to retry the data transaction of the bus master. Alternatively, the wait register is adapted to couple the delay input to the bus master such that the bus master initiates a subsequent access to the PCMCIA device at the expiration of the latency period in order to efficiently complete the subsequent access to the target PCI agent. Alternatively, the wait register is coupled to an arbiter such that the arbiter does not grant the local bus to the bus master for a subsequent access until the expiration of the latency period.</p> |
