发明名称 |
METHOD AND APPARATUS FOR JUMP CONTROL IN A PIPELINED PROCESSOR |
摘要 |
An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of permitting programmer control of jump instruction interlocks is disclosed. In one embodiment, a minimum of one cycle is required between an instruction that sets flags and a branch taken as a result of those flags; an interlock is used to detect a branch preceded by an instruction setting the flags to ensure that the instruction immediately preceding the branch can not affect the branch outcome. In a second embodiment, a jump instruction following a flag setting instruction whose flags may affect the outcome of the jump is stalled until all flags are set. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned interlocks is disclosed. Exemplary gate logic synthesized using the aforementioned methods, and a computer system capable of implementing these methods, are also described.
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申请公布号 |
WO0070444(A3) |
申请公布日期 |
2001.08.09 |
申请号 |
WO2000US13030 |
申请日期 |
2000.05.12 |
申请人 |
ARC INTERNATIONAL U.S. HOLDINGS INC. |
发明人 |
HAKEWILL, JAMES, ROBERT, HOWAR;SANDERS, JON |
分类号 |
G06F9/318;G06F9/32;G06F9/38;G06F17/50;(IPC1-7):G06F9/32 |
主分类号 |
G06F9/318 |
代理机构 |
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主权项 |
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地址 |
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