| 摘要 |
Magnetic tunnel junction random access memory parallel-parallel architecture wherein an array of memory cells is arranged in rows and columns with each memory cell including a magnetic tunnel junction and a control transistor connected in series. The array of memory cells is constructed with a plurality of columns and each column includes a global bit line coupled to a control circuit. Each column further includes a plurality of local bit lines coupled in parallel to the global bit line and a plurality of groups of memory cells, with each group including a plurality of memory cells connected in parallel between the local bit line and a reference potential.
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