| 摘要 |
The present invention relates to a semiconductor memory device; and, more particular, to DRAM and SRAM having a common pin for address and data signals. A semiconductor memory circuit in accordance with the present invention has at least one common signal input terminal for receiving data signals and address signals, wherein the common signal input terminal is coupled to a plurality signal paths and a signal path selector for selecting one of the plurality signal paths in response to a write enable signal, a read enable and a control signal from a memory controller. The signal path selector has a plurality of buffers on the signal paths and the signal path selector selects one of the buffers in response to a write enable signal, a read enable and a control signal from a memory controller.
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