| 摘要 |
Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.
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