| 摘要 |
Trench capacitors are arranged in the form of a matrix at a constant pitch in row directions while being sequentially shifted between adjacent rows by a predetermined pitch. An element isolating insulator film is formed so as to surround active regions, each of which is adjacent to adjacent two capacitors in row directions, together with a partial region of the two capacitors. Transistors, which have gate electrodes continuously formed as word lines, are formed so as to be adjacent to the respective capacitors. One of the source and drain diffusion layers is connected to the capacitor node layer of a corresponding one of the capacitors via a connecting conductor. The other of the source and drain diffusion layers serves as a bit line contact layer shared by adjacent two transistors in the row directions, so that bit lines connected to the respective bit line contact layers in the row directions are formed. Three word lines are provided between adjacent bit line contact layers. By providing such a layout of a DRAM cell array, it is possible to decrease the area occupied by a unit memory cell while ensuring the capacity of a trench capacitor.
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