发明名称 DYNAMIC LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To operate a CMOS circuit at a higher speed than in a case where a static-type circuit is employed at low supply voltage, thereby reducing static leak current caused by MOS transistor having low threshold voltage during a sleep mode. SOLUTION: A domino circuit is constructed by interchangeably connecting a unit dynamic circuit comprising an nMOS pull down network transistor of low threshold, an nMOS discharge transistor of low threshold and a pMOs precharge transistor of high threshold, and a static CMOS inverter comprising a pMOS transistor of low threshold and an nMOS transistor of high threshold. During a sleep mode, all input data to the domino circuit and *ST1 are fixed to '1', so that the precharge transistor is brought out of conduction and other discharge transistors are brought into conduction. During operating, all input data to the domino circuit is kept as they are, while during precharging, the precharge transistor is brought into conduction with the discharge transistor being brought out of conduction, which is reversed during logic evaluation.
申请公布号 JP2001211067(A) 申请公布日期 2001.08.03
申请号 JP20000016266 申请日期 2000.01.25
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 FUJII KOJI
分类号 H03K19/096;(IPC1-7):H03K19/096 主分类号 H03K19/096
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