REGISTER ACCESS SYSTEM IN ATM COMMUNICATION

摘要

PROBLEM TO BE SOLVED: To facilitate the register test of a PHY layer device 1 and also to shorten the test time. SOLUTION: When the access test of a register part 10 in a device 1 is performed, a register access system is provided with a bus extraction control part 12 for extracting R/W access data from the pay load area of a reception frame data to the register part 10 and with a bus insertion control part 13 for storing address data AD2 and reading data RD which is read from the register part 10 based on access timing signals T5-T9 and for inserting them to a transmission frame data part SD in addition to transmitting/receiving data processing parts 11 and 14. The TM signals changeover a route between an external CPU 2 and the register part 10 into the route between the control part 12 and the register part 10 so that high speed writing/reading is performed in the register part 10 by reception frame data and a clock.