发明名称 DELAY CIRCUIT FOR POWER SUPPLY
摘要 PROBLEM TO BE SOLVED: To provide a power supply delay circuit that can control rise times of multiple output voltages and reduces an EMI(electromagnetic interference) noise, and the delay time of which is accurate. SOLUTION: The circuit has two regulators (1 and 2) including transistor converting and outputting an input voltage (5 V) to the specified voltages (2.5 V and 3.5 V). Each regulator has at least more than two input terminals. In the regulator 1, the input voltage (5 V) is charged, to an input terminal, the output voltage (2.5 V) from the regulator 2 is charged to other input terminal 61.
申请公布号 JP2001209438(A) 申请公布日期 2001.08.03
申请号 JP20000019608 申请日期 2000.01.28
申请人 NEC CORP 发明人 SHIGENO TENSHIYUU
分类号 G05F1/00;G05F1/10;(IPC1-7):G05F1/00 主分类号 G05F1/00
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