发明名称 LAYOUT DESIGN METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To make a semiconductor device uniform in wiring data rate through its layout and to uniformly carry out etching or the like in manufacturing a semiconductor device. SOLUTION: A wiring data rate is checked (S2) after a normal wiring is laid (S1) so as to easily render a wiring data rate indicating the wiring density of a certain layout region uniform in the layout design of a semiconductor device. When it is found after an automatic layout/wiring is made that a region is low in wiring data rate (S3), dummy terminals are arranged on a power supply wiring or a ground wiring (S11 and S12), and a wiring connecting the dummy terminals together is additionally provided through an automatic layout system (S13 to S16), by which wirings can be set in a proper range of data rate.
申请公布号 JP2001210720(A) 申请公布日期 2001.08.03
申请号 JP20000018270 申请日期 2000.01.27
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 YOSHINAGA JINKO
分类号 H01L27/04;G06F17/50;H01L21/82;H01L21/822;H01L23/522;(IPC1-7):H01L21/82 主分类号 H01L27/04
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