| 摘要 |
PROBLEM TO BE SOLVED: To form a source and a drain, which are respectively formed on the upper and lower gate electrodes of an field-effect transistor, in a state, where the source and drain are aligned with each other to minimize parasitic capacitance which impairs high-speed operation of the field-effect transistor. SOLUTION: A field-effect transistor is constituted of a second support substrate, a lower gate embedded in an insulator formed on the second support substrate, an insulating layer formed on the lower gate, a semiconductor layer formed on the insulating layer, an insulation layer formed on the semiconductor layer, an upper gate formed on the insulation layer, source and drain electrodes separated from each other by the insulation layer, an upper gate electrode and a lower gate electrode.
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