| 摘要 |
A semiconductor memory device having an operation delay function of a CAS command, and a buffer and a signal transmission circuit which are applied to the semiconductor memory device, are provided. The signal transmission circuit includes a plurality of transmission units each for delaying an input signal by a different number of delay clock cycles. The transmission unit includes a transmission switch and a clock delay unit. The semiconductor memory device can delay a received signal for different numbers of delay clocks in response to first through third control signals. Therefore, a predetermined delay time between when a row-type command is received and when a column-type command is received can be shortened.
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