| 摘要 |
A sequential access memory structure (50) includes an output (20) bus and a plurality of sequential access memories (10a, 10b, 10c, 10d), each of which is connected to the output bus (29). Each memory (10a, 10b, 10c, 10d) includes a memory array (12) having a plurality of sequentially readable memory elements, a carry output (40) for producing a carry signal when reading of the array (12) has been substantially completed, and a carry input (42) for causing reading of the array (12) in response to a carry signal. The carry output (40) of each memory (10a, 10b, 10c, 10d) is connected to a carry input (42) of one other downstream memory respectively in a chain arrangement, and the carry signals cause the arrays (12) to be read sequentially onto the output bus (20). Each memory (10a, 10b, 10c, 10d) further comprises a read-write storage (14, 16) connected between the array (12) and the output bus (29), the storage (14, 16) including a plurality of sections (10a, 10b, 10c, 10d). Data from the array (12) is loaded into one section of the storage (14, 16) while data is being read from another section of the storage (14, 16) onto the output bus (29). The sections of memory elements (12b, 12c) in the array (12) comprise half-pages. The storage (14, 16) comprises two sections, each of which has a half-page of memory elements, and the carry output produces the carry signal prior to reading data from a last half-page (12c) of the array (12) out of the storage (14, 16) onto the output bus (29). Data from the last half-page (12c) is read onto the output bus (29) while data from a first half-page of an array (12) of a next downstream memory (10a, 10b, 10c, 10d) is being loaded into its storage (14, 16).
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