| 摘要 |
A feed-back inverter for use in a jam latch is disclosed. The feed-back inverter includes a first pair of NMOS and PMOS devices connected in parallel along a charge/discharge path of the inverter. A second pair of NMOS and PMOS devices are connected in parallel with the first pair but are outside of the charge/discharge path of the inverter. The first pair of devices has relatively short device lengths, whereas the second pair has relatively long device lengths. By providing devices along the charge/discharge path of the inverter that have relatively short device lengths, the capacitive load of the devices along the charge/discharge path is relatively low and the switching times are relatively short, resulting in relatively little data-power dissipation during voltage transitions. However, by providing an additional pair of complimentary devices with relatively long device lengths within the feedback inverter but outside of the charge/discharge path, the overall current drawn by the feed-back inverter is kept low in comparison with that of other inverters of the jam latch such that the other opposing, inverters dominate and permit reliable latching of data. Specific implementations are disclosed for use with two-phase and single-phase clock signals and for use within circuits having either relatively high or low voltage source levels. |
