Semiconductor memory device capable of reducing data test time in pipeline

摘要

A semiconductor memory device capable of reducing a data test time in a pipeline is provided. The semiconductor memory device has a pad, data lines, and a data port (DQ) block including a plurality of memory cells. The semiconductor memory device includes a pipeline adapted to output data from selected memory cells of the plurality of memory cells in the DQ block to the pad via the data lines. The pipeline includes a plurality of unit pipeline cells (UPLs) connected in a series. Each of the UPLs is further connected to each of the data lines and is adapted to latch the data, wherein the data is transmitted to a subsequent UPL in the series, if any, so as to sequentially transmit the data to the pad. A comparison controller is connected to a last UPL in the series. The comparison controller is adapted to perform a test for defects in the data and to provide a result of the test to the pad during a test mode, whereby the presence or absence of defects in the DQ block is verified in synchronization with an edge of a clock signal.