| 摘要 |
An architecture for a state machine used to control the data processing operations performed on the memory cells contained in a memory array. The architecture is designed to control the performance of the operations and sub-operations used to erase and program the memory array. The architecture of the present invention does not utilize separate state machines for each primary operation, but instead is based on a single state machine which is capable of controlling the various functions common to the data processing operations carried out on the memory cells. A sequencer which acts upon commands input from an external microprocessor is used to determine which set of sub-operations or functions needs to be performed to implement the commanded operation. The sequencer activates a timer which acts to trigger the functions controlled by a loop controller as they are needed for a particular operation. The sequencer provides input signals to the loop controller which are used to determine the parameters of the signals generated by the loop controller. These signals are used to control the high voltage supplies which produce the pulses for erasing or programming the cells and other modules used during the data processing operations.
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