| 摘要 |
A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage. In a preferred embodiment, the memory cell read/write voltage control circuit further includes a wordline voltage control circuit for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation. In another preferred embodiment, the memory cell read/write voltage control circuit further includes a memory-core power supply voltage (CVdd) control circuit for providing a higher CVdd voltage in a read operation and a lower CVdd voltage in a write operation. In another preferred embodiment, the memory cell read/write voltage control circuit further includes a memory-core ground voltage (CVss) control circuit for providing a lower CVss voltage in a read operation and a higher CVss voltage in a write operation.
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