| 摘要 |
A signal processor for pipeline processing which can effectively avoid deterioration of the processing efficiency caused by branch instructions and methods thereof: wherein when obtaining a result that an instruction decoded in an ID module is a branch instruction, determination is made as to branch existence in an EX module in the next cycle, and an instruction in a branch destination and an instruction in a non-branch destination are fetched simultaneously in an IF module; consequently, in the next cycle, in response to the result of the branch existence, one of the fetched instructions of the branch destination or the non-branch destination is selected and is then decoded in an ID module.
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