Self-test for charge redistribution analog-to-digital converter

摘要

An analog-to-digital converter has a binary weighted capacitor array with one plate of each capacitor connected at an input to a comparator and successive approximation logic circuitry provided for selectively connecting the capacitors to high reference, low reference or analog input signal voltage to develop a digital output in a successive charge redistribution conversion process. An on-board test data generator provides a test input voltage signal for a test mode. The other plate of each capacitor is selectively connected to the high or low reference voltage to charge the capacitors separately according to a prestored or externally supplied test pattern sequence. The digital output obtained from applying the usual sample, hold and charge redistribution process to the internally supplied test signal is compared to an expected digital output for an input signal corresponding to the predetermined test pattern sequence.