Internal clock generating circuit of synchronous type semiconductor memory device and method thereof

摘要

An internal clock generating circuit of a synchronous type semiconductor memory device includes a transmission part for transmitting a first clock enable signal in response to applying a first level of a first clock signal. It also includes a latch part for latching the first clock enable signal transmitted from the transmission part. A gating part gates the latched first clock enable signal with the first clock signal to generate a second clock signal as an internal clock signal for the memory device. This reduces a time lag by which the speed of the internal clock is synchronized with the external clock signal.