发明名称 |
Method and apparatus for 3-stage 32-bit adder/subtractor |
摘要 |
An apparatus that takes two N-nary operands and selectably performs either addition or subtraction on them to produce an arithmetic result and a carry indicator. Carry-lookahead logic is utilized to create HPG signals for each N-nary dit of the intermediate sum of the two operands and also to create "block" HPG indicators for blocks of dits. In the preferred 1-of-4 embodiment, subtraction may be implemented as four's complement addition. The value of each dit of the intermediate sum is incremented by one before final output if a carry has propagated into the dit.
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申请公布号 |
US6269387(B1) |
申请公布日期 |
2001.07.31 |
申请号 |
US19980206463 |
申请日期 |
1998.12.07 |
申请人 |
INTRINSITY, INC. |
发明人 |
PETRO ANTHONY M.;BLOMGREN JAMES S. |
分类号 |
G06F7/49;G06F7/50;G06F7/508;(IPC1-7):G06F7/50 |
主分类号 |
G06F7/49 |
代理机构 |
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代理人 |
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地址 |
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