发明名称 |
Semiconductor device and method of fabricating the same |
摘要 |
A DRAM control circuit or a test circuit describing a delay control cell is prepared. Automatic placement and routing is performed in relation to this circuit. Circuit simulation is executed at a step ST16. Delay control is performed with the delay control cell on the basis of a simulation result. Alternatively, delay control is performed with a circuit of the delay control cell on the basis of a test result. Thus, automatic placement and routing of at least either the DRAM control circuit or the test circuit provided in a DRAM is enabled.
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申请公布号 |
US6269280(B1) |
申请公布日期 |
2001.07.31 |
申请号 |
US19980113029 |
申请日期 |
1998.07.13 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MIYANISHI ATSUSHI;YAMAZAKI AKIRA |
分类号 |
H01L21/82;G06F17/50;G11C11/401;H01L21/8242;H01L27/10;(IPC1-7):G06F17/50 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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