发明名称 |
Method for operating a non-blocking hierarchical cache throttle |
摘要 |
A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level, receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level. In response to the monitoring step the second cache level generates a stall signal thereby stalling the picking process.
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申请公布号 |
US6269426(B1) |
申请公布日期 |
2001.07.31 |
申请号 |
US19970881724 |
申请日期 |
1997.06.24 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
HETHERINGTON RICKY C.;WICKI THOMAS M. |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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