| 摘要 |
PROBLEM TO BE SOLVED: To provide a circuit in a chip receiving data synchronously with a clock, that takes synchronization between the data and the clock with high accuracy by delaying only the clock without delaying the data. SOLUTION: The circuit to synchronize the data and the clock is provided with a 1st circuit 2 that detects a phase shift between an input signal (DATA) and a clock (ϕi), a 2nd circuit 3 that converts the detected phase shift into a control voltage for a delay time, a 3rd circuit 4 that produces a delay in response to the control voltage to delay the clock (ϕi) and to produce a sampling clock, and a 4th circuit 5 that receives the input signal in the timing of the sampling clock. The 2nd circuit 3 has a means that discretely controls a delay time and the 3rd circuit 4 has a storage element and a 5th circuit inside to detect a control error. |
