| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a slip control circuit that can forcibly ensure an ideal phase difference between a write phase and a read phase to/from an elastic storage memory. SOLUTION: A mutual phase difference between address values outputted from a 1st write address counter 3, a 2nd write address counter 4, and a read address counter 5 is forcibly shifted within a buffer capacity set by a buffer capacity setting section 8 through the operation of a 1st load selector 11, a 2nd load selector 12, an offset selector 13 and a write address selector 6 on the basis of a phase adjustment timing signal, so that transmission of output data is started from a state where the write phase from a frame memory 2 and the read phase to the frame memory 2 are shifted by 180 degrees without fail.</p> |
