| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can reduce a skew of a rising part of a clock pulse without the increase of the size of the circuit. SOLUTION: A plurality of buffers 11-13 are arranged and connected into a tree-shape from a leading end to a finishing end. The input terminals of the buffers 11 on the leading end are connected to an output terminal of an inverter 14. The output terminal of the buffer 13 on the finishing end is connected to an input terminal of an inverter 15. The respective buffers 11-13 output inputted pulses without reversing them. Clock signals are inputted to the input terminal of the inverter 14. The output terminal of the inverter 15 is connected to a clock terminal CLK of a D-type flip-flop 16. The inverters 14 and 15 reverse inputted pulses and output them.</p> |
