| 摘要 |
PROBLEM TO BE SOLVED: To lock a PLL without the need for a high-speed operation even when data with different frequencies assigned to a consecutive slot are sent/ received. SOLUTION: The PLL controller is provided with a timing adjustment circuit 17 that receives detection of a transmission reception state to adjust output timing of a PLL load signal and a PLL enable signal, a PLL enable signal generating counter 19 that counts the number of bits of data loaded to the PLL to set an enable period of the PLL, an AND circuit 22 that generates the PLL enable signal and a PLL clock masked for the enable period, and a PLL designation counter 12 that sequentially designates any PLL among a plurality of PLLs to which the data are loaded after a lapse of each enable period.
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