| 摘要 |
PROBLEM TO BE SOLVED: To provide a simulation method for a logic circuit, with which a time for simulation to be performed after a change applied only to the block of one part is shortened in the simulation of a logic circuit composed of plural blocks. SOLUTION: In the simulation for inputting circuit information 101 and a test pattern 102, when only the block designated by block designation information 105 is changed, by using information 103 and 104 of signals prepared in previous simulations, a simulation time is reduced.
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