| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the complicated arrangement of Z-word lines can be avoided, a structure with an odd-number of blocks can be realized and a high speed operation, cost reduction, current consumption reduction and reduction in the number of layers without a three-dimensional crossing can be realized in a sub-bit line selection system, wherein a hierarchical bit line structure is provided and sub-bit lines on a data side and sub-bit lines on a reference side correspond one-to-one to each other. SOLUTION: This semiconductor device is a single chip microcomputer. In a memory mat 11 of a memory module, dummy cells DMC21-DMC24 and DMC15-DMC18, which have loads equivalent to loads on a data side of a pair of bit lines Mb1 and Mb2 and are exclusive for a reference side, are arranged on both sides (the uppermost part and the lowermost part) in a bit line direction. Z-word lines 21, 22 nd 23 for selecting sub-bit lines on both data side and the reference side are arranged as single straight lines respectively.</p> |
