发明名称 |
SEMICONDUCTOR MEMORY AND ITS CONTROL METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory whose chip area can be reduced. SOLUTION: A control circuit is constituted so that a sense amplifier 25a is activated after a column gate 71 is turned on at the time of a write operation and data from a data bus line DB are applied to one side of the input/output terminal of the sense amplifier 25a connected to a pair of bit line BL, /BL. The activated amplifier 25a amplifies the potential of the bit line BL connected to an input/output terminal T1 to which data are supplied up to a potential of the data and amplifies the potential of an inversion bit line /BL up to the inversion potential of the data.
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申请公布号 |
JP2001202781(A) |
申请公布日期 |
2001.07.27 |
申请号 |
JP20000009249 |
申请日期 |
2000.01.18 |
申请人 |
FUJITSU LTD;FUJITSU VLSI LTD |
发明人 |
TOUHO MITSUHIRO |
分类号 |
G11C11/409;G11C7/06;G11C7/10;G11C11/407;(IPC1-7):G11C11/409 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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