发明名称 |
Clock synchronization circuit and semiconductor device having the same |
摘要 |
A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.
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申请公布号 |
US2001009275(A1) |
申请公布日期 |
2001.07.26 |
申请号 |
US20010757792 |
申请日期 |
2001.01.11 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JUNG YEON-JAE;LEE SEUNG-WOOK;SHIM DAE-YUN;KIM WON-CHAN |
分类号 |
G11C8/18;G06F1/12;G11C7/22;G11C11/4076;H03L7/07;H03L7/081;H03L7/089;(IPC1-7):H01L47/00 |
主分类号 |
G11C8/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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