| 摘要 |
<p>The problems associated with slow timing recovery in an ATM receiver (200) are overcome by detecting (in 201) the transmission rate of a received bit stream and periodically detecting the transmitted Enc_CR values, which are used to calculate additional estimated clock reference (Est_CR) values between the actual transmitted Enc_CR values. The Est_CR values are then used along with the actually received Enc_CR values to generate a phase locked loop (PLL) error signal (TC_ERROR), wherein the PLL(208,210) is caused to converge more rapidly. In one embodiment, the TC_ERROR values are generated for each received cell or packet instead of only for each received Enc_CR value and, consequently, timing recovery is significantly speeded up. Additionally, the Est_CR values can be adjusted to minimize the effects of lost cells, as well as, drift in the transmission rate. <IMAGE></p> |
