| 摘要 |
The present invention relates to a frequency divider having an adjustable divider ratio (TV). Such circuits are subject to requests for ever higher clock frequencies. For fulfilling said requests, the inventive circuit generates the output signal (OUT) block by block, converts said signal into a sequential signal in a parallel-serial converter (MUX) and outputs said sign al bit by bit, whereby said converter is situated on the output side. The essential part of the frequency divider circuit can thus be operated by mean s of a frequency (C4) that is slower than the input frequency (C) and, as a result, higher input frequencies are possible.
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