CONTROL OF TRANSISTOR PERFORMANCE THROUGH ADJUSTMENT OF SPACER OXIDE PROFILE WITH A WET ETCH

摘要

Methods of patterning sidewall spacers are provided. In one aspect, a method of fabricating a circuit device (10) includes forming a gate (14) on a substrate (12) and forming a first oxide spacer (18a) and a second oxide spacer (18b) adjacent to the gate (14). The width of the gate (14) and the first and second oxide spacers (18a), (18b) is measured. The widths of the first and second oxide spacers (18a), (18b) are trimmed if the width of the gate (14) and the first and second oxide spacers (18a), (18b) exceeds a preselected maximum value by exposing the first and second oxide spacers (18a), (18b) to a solution of NH4OH, H2O2 and H2O for a preselected time and rinsing with deionized water. Spacer width may be finely tuned to reduce the risk of weak overlap and to improve device characteristics through shorter channels.