| 摘要 |
PURPOSE: To provide a reliability verifying method for semiconductor integrated circuit, with which the reliability of a semiconductor integrated circuit in large scale can be verified without omission. CONSTITUTION: An intra-cell total input/output capacity sum Cio of a selected cell is found while utilizing the input load capacity and output load capacity of cells registered in a cell library data base 1A in a step S12 and inter-cell wiring capacity Cic is found in a step S13. Afterwards, output terminal load capacity COUT is found by adding the intra-cell total input/output load capacity sum Cio and the inter-cell wiring capacity Cic in a step S14. Then, a fault rate FOUT of inter-cell wiring is found on the basis of the output terminal load capacity COUT in a step S15, and a fault rate Fcell is provided by applying a calculation expression registered in the cell library data base 1A on the basis of the output terminal load capacity COUT in a step S16. Continuously, the sum of the fault rate Fcell and the fault rate FOUT is found as a total fault rate Ftotal in a step S17.
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