| 摘要 |
A chip scale package mainly comprises a semiconductor chip disposed on an upper surface of a substrate and sealed by a package body. The package body comprises a resin base material divided into a first region and a second region. The resin base material contains a plurality of filler particles having the percentage by weight of the filler particles in the first and second regions being different. Thus, in accordance with the present invention, the package provides better buffering effect for stresses due to CTE mismatch between the substrate and the chip, and significantly reduces the moisture from surrounding diffusing into the package thereby reducing the problems of delamination or die-cracking.
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