| 摘要 |
A vector-processor SIMD RISC computer system uses virtual addressing and overlapped instruction execution. Indicators for each of the architected registers assume different states when an instruction, overlapped with a vector memory-reference instruction, has or has not read from or written to a particular register. Multiple overlapped vector memory-reference instructions are assigned separate sets of indicators. Indicators in a certain state prevents a subsequent overlapped instruction from writing to its associated register. |
