发明名称 |
ROM data verification circuit |
摘要 |
A ROM data verification circuit has a DMAC (2) for reading out data stored in the ROM (1) when a CPU (3) abandons to use an address bus (5) and a data bus (6), for dividing the data read into a plurality of divided data, and for outputting the divided data into a plurality of output ports (4) designated by addresses generated by the DMAC (2). |
申请公布号 |
US6266626(B1) |
申请公布日期 |
2001.07.24 |
申请号 |
US19980222873 |
申请日期 |
1998.12.30 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YUSA TERUKAZU;KUROIWA MICHIAKI;HIRATE KOJI |
分类号 |
G06F13/28;G06F13/14;G06F13/36;G11C29/52;(IPC1-7):G11C7/00 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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